verilogsystem-verilog

Does the SystemVerilog standard allows mixing with Verilog files?

Does the SystemVerilog standard permit to mix SystemVerilog files (.sv) with Verilog files (.v)?

Solution

  • SystemVerilog is 100% backward compatible with Verilog with one major exception: additional reserved keywords. This means any working code in Verilog will compile and behave the same SystemVerilog as long as the Verilog code does not use any SystemVerilog keywords like logic or bit.

    SystemVerilog does provide compiler directives `` `begin/end_keywords to un-reserve those keywords regardless of any tool specific command line behavior. But most tools automatically provide that capability by looking at the extension of the file on the compilation command line.