verilogbitstream

1 bit stream in verilog


I have 6 gas sensors which are connected to an Arduino uno board which I use as an ADC. The output of each sensor will be a number between 0 and 1023. The data is transferred from the Arduino to an Altera FPGA for processing.

I send the binary form of the number to the output pin of Arduino (serial data) and by receiving a 'write' signal from FPGA, this data will transmit serially to an input port of FPGA, at roughly 10kHz (0.1ms period).

How can the original number be reconstructed in the FPGA after the serial transmission?


Solution

  • To convert Serial to Parallel, you need some way to identify the end or start of sequence. Something like the following should get you off to a start:

    input            clk;
    input            end_of_sequence;
    input            sdata;
    output reg [9:0] result;
    //10 bit transmission
    
    reg [9:0] pdata;
    
    always @(posedge clk) begin
      // Shift serial data in
      pdata <= {pdata[8:0, sdata};
    end
    
    always @(posedge clk) begin
      if (end_of_sequence ) begin
        // at end of shifted data store the full parallel word
        result <= pdata;
      end
    end