Why is `-3'd300>5000` true in Verilog?

`timescale 1ns / 1ps
module m_top 
(
input GCLK,//100MHz,Y9
output reg o_out2,
inout io_data
);
  

initial begin
    if(-3'd300>5000)begin
       $display("%b",-3'd300);//00000000000000000000000000000100
       $display("%b",5000);//00000000000000000001001110001000
      end
end
endmodule

In this Verilog script, -3'd300>5000 is true, which means 00000000000000000000000000000100>00000000000000000001001110001000, where is the problem?

Three problems:

1. The width before the ’ represents the number of binary digits, which is the width of the value’s representation in binary. You should have received a warning message about the number of numeric literals. The value is truncated to 3’b100.

2. You are comparing an unsigned number -3’b100 with an signed number 5000. In this scenario, all operands get treated as unsigned when there is a combination of unsigned and signed numbers.

3. You are comparing a 32-bit operand with a 3-bit operand. Before the negation operator - is applied, the width of the 3-bit operand gets extended to 32 bits.

   So the actual comparison is 32'hfffffffc > 32'h00001388.