I am a newbie to verilog. I have constructed my code using integer inputs and outputs in vhdl. Now i want to construct the same code in verilog. But I came to know that the input ports in verilog cant be of integer type. What can be done. I would prefer an answer which is synthesizable.
vhdl code:
LIBRARY ieee;
USE ieee.All;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
ENTITY adder_5 IS
PORT (
a : IN integer ;
b : IN integer;
c : OUT integer
);
END adder_5;
ARCHITECTURE add OF adder_5 IS
BEGIN
c<= (a rem 32) + (b rem 32);
END add;
Integers in Verilog and integers in VHDL are not the same thing. In VHDL an integer is a signed 2-state type with at least 32 bits. In Verilog an integer is a 32-bit signed 4-state variable. So, in Verilog,
integer a;
and
reg signed [31:0] a;
are equivalent. In Verilog input ports had to be net types, so integer input ports were not allowed. However, output ports were allowed to be variables, so an output port could be an integer. So, you can replace VHDL input integers with reg signed [31:0] and output integers with integer and your code in Verilog is
module adder (input wire signed [31:0] a, b, output integer c);
always @(*)
c = a%32 + b%32;
endmodule
or perhaps for consistancy:
module adder (input wire signed [31:0] a, b, output reg signed [31:0] c);
http://www.edaplayground.com/x/5PZe
So, integers were allowed in output ports but not input ports.