vhdl

What is the utility of a "clock'event" if the sensitivity list has a single signal and is tested at 1?

I was wondering what is the difference between

process (clk)
if (clk = '1') then

and

process (clk)
if (clk'event and clk = '1') then

I thought the sensitivity list defined on which signals a state change would be monitored so if I am right then the clk'event is redundant.

I have made a simple simulation to verify what I thought and it apparently confirmed my opinion.

Solution

  • Yes, you are right, during a simulation both code snippets work identically.

    But during synthesis all signals which are read in the process are added implicitly to the sensitivity list. This means if there is the assignment B<=A; inside the process, A is added to the sensitivity list and at any time when A is changed B will also change, if clk='1'.

    So without clk'event the code describes a latch and not a flipflop in synthesis.