VHDL error, unsigned on the LHS and RHS of assignment

Questa gives this error (compiling with -2008 on EDA Playground)

-- Compiling architecture rtl of foo
** Error: design.vhd(31): Type error resolving infix expression "xnor" as type ieee.NUMERIC_STD.UNSIGNED.
** Note: design.vhd(31): (vcom-1499) Aggregate with a single element association must use named association.

for this sample code

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity foo is
  port(
 clk  : in std_logic;
 reset: in std_logic;
 din  : in std_logic;
 dout: out unsigned(7 downto 0)
      );
end entity foo;

architecture rtl of foo is

signal prbs_fb  : unsigned(0 downto 0);
-- changing to std_logic makes the error go away signal prbs_fb  : std_logic;

begin
  
  process (clk)
  begin
    if reset = '1' then
      dout <= "00000000";
    elsif rising_edge(clk) then
      dout(7 downto 0) <= dout(6 downto 0) & prbs_fb;
    end if; 
  end process;
    -- below is line 31
    prbs_fb <= dout(7) xnor dout(5) xnor dout(4) xnor dout(3);
          
end architecture;

I can make the error go away by changing the type of signal prbs_fb to std_logic.

The type definition unsigned(0 downto 0) makes more sense to me because the RHS of the assignment is unsigned. It seems like the code is inferring a single bit of unsigned on the LHS of the assignment and a single bit on the RHS of the assignment.

Why is line 31 considered an aggregate? The output of the logical operators should be one bit?

The message produced by Cadence is different; but its also unhappy about something.

    prbs_fb <= dout(7) xnor dout(5) xnor dout(4) xnor dout(3);
                                                    |
xmvhdl_p: *E,EXPTYP (design.vhd,31|52): expecting an expression of type UNSIGNED 87[8.3] 93[8.4].
xrun: *E,VHLERR: Error during parsing VHDL file (status 1), exiting.

This also eliminates the error, however its not clear why VHDL would require named association (the 3rd edition Ashenden book section 4.12 Array Aggregates calls this 'named association') for the assignment of a single element array?

prbs_fb <= ( 0 => dout(7) xnor dout(5) xnor dout(4) xnor dout(3) );

VHDL is strongly typed. prbs_fb is an array type, and dout(n) are single elements of the dout array, which return scalar types std_logic. The result of all of the xnor operators are all single std_logic , which is not an array type, and hence cannot be assigned back to the array type.

Using the aggregate assignment (not named association as you call it - named association is for mapping of generic or interface lists) then implies that the returned type should be an array type, and can then infer that this array type is unsigned from the assignment.

It does not matter that it is only a single element - it is still an array type, and hence requires the array type for the assignment.