Is it possible for a 8bit CPU to read memory in less than 3 clock cycles? I know that the 6502 works with an asynchronous memory but what about other 8bit CPUs with clocked memories? Do I need a clock divider to make the CPU slower?
My understanding is that during cycle 1: CPU outputs an address, during cycle 2: memory reads the address then gives the corresponding byte, and during cycle 3: CPU finally receives byte. Is this correct?
My understanding is that during cycle 1: CPU outputs an address, during cycle 2: memory reads the address then gives the corresponding byte, and during cycle 3: CPU finally receives byte. Is this correct?
That's not quite right. In particular, the CPU must "receive" the byte in the same cycle that the memory has "given" it. Generally, the value is latched with a rising or falling clock edge.
What exactly takes place depends on the instruction that's executing. For example, an LDA immediate takes two cycles. The first cycle, the CPU reads the opcode. The second cycle, the CPU reads the operand and stores it in the accumulator.
Another example: LDA zeropage. The CPU reads the instruction in the first cycle. It reads the address in the second cycle. Then it reads the datum into the accumulator on the third and last cycle of the instruction.
Notice how each cycle is a memory access on the 6502. An address is output, and an 8 bit value is read in or written out. Always.