verilogmipspipelinecpu-architecturemips32

forwarding data in which stage in mips piplined

while reading this lecture I have read this slide enter image description here

and can't imagine why forwarding to Id stage is pointeless while I saw other resource with the following design which does the opposite of proposed design

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and I want comprehend if there is good or bad approach regarding this concept as I think both of can work while in most references and text books seem to be like the first one but they need to forward to ID stage when branch hazards occur and I wonder why the other forwards needs to be in EX stage and just move all of them to ID with branch forwards Ruther than adding extra multiplexers and signals

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source 1 : https://www.cs.cornell.edu/courses/cs3410/2012sp/lecture/10-hazards-i.pdf

source 2 : https://faculty.kfupm.edu.sa/coe/mudawar/coe233/lectures/13-PipelinedProcessorDesign.pdf

source 3: Harris book and same design in Hennessy book

Solution

  • as erik pointed out in comments and the answer I could reach that the textbooks assumes that register file can read and write in same cycle (write on negative edge and read on positive edge )and this makes it possible to forward to EX as the data will be ready next cycle .

    while the other lectures assumes that register file can only perform reading and writing in full cycle , to get data to EX from registers you will have to wait extra cycle and stall the pipeline , so its easier to forward to Decode stage in this case.

    assumption of textbook is possible via verilog as below

    module regfile(input  logic        clk, 
               input  logic        we3, 
               input  logic [4:0]  ra1, ra2, wa3, 
               input  logic [31:0] wd3, 
               output logic [31:0] rd1, rd2);

  logic [31:0] rf[31:0];

  // three ported register file
  // read two ports combinationally
  // write third port on rising edge of clk
  // register 0 hardwired to 0
  // note: for pipelined processor, write third port
  // on falling edge of clk

  always_ff @(negedge clk)
    if (we3) rf[wa3] <= wd3;    

  assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
  assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
endmodule

    Code taken from repo below

    https://github.com/HMS-ELKHOLY/pipline_mips

    but the design of the lecture assumes ordinary registers that their values need to be written or read in full cycle