In the below module, ideally cnt, width & start should be inout port, instead of output port.
But I tried with those ports as output ports and still I am able to run it without any error. So can inout and output ports be used interchangeably in Verilog?
If no, then what is the exact criteria, where inout port must be used (output port can't be used in that case)?
module (clk, rst, cnt, start, width, signal);
input clk, rst, signal;
output reg [11:0] cnt, width;
output reg start;
always @(posedge clk or negedge rst)
begin
if(~rst)
begin
cnt <= 0;
start = 0;
width <= 'h271;
end
else
begin
if(signal)
begin
width <= (start) ? width : 'h271;
start = 1;
end
cnt <= (start) ? (cnt + 1) : cnt;
end
end
endmodule
Note - I know, that with inout ports, I need to modify the code, as inout ports can't be of reg type. But I am here asking about just type of ports only.
Port direction is basically advisory in Verilog, and this hasn't changed in SystemVerilog. This is a historical isue, and is related to how Verilog XL (the first Verilog simulator) did port collapsing; basically, everything is an inout. when the '95 LRM was written this existing behaviour was basically documented. In 1364-2005 this appears in 12.3.8 as
A port that is declared as input (output) but used as an output (input) or inout may be coerced to inout. If not coerced to inout, a warning has to be issued.
In practice, everything ends up as an inout, and you may or may not get a warning. So, you can do pretty much anything in a simulator, but a linter or a synthesiser should pick up any logical connection errors for you (if it doesn't, it's pretty useless). There are other specific non-direction rules in the following sections - input and inout ports have to be of net type, and so on.