Rotating shift register with d flip-flops verilog

Currently I'm trying to do this project, and I'm stuck on the shift register. The thing is, I'm fairly certain they want us to implement this with d flip-flops, but I've only ever seen simple if/then shifters.

So far I've gotten each led to simulate lighting up for the duration of the reset signal, as I've used that for input. However, the whole goal of this is to have each led light up for only one tick of the clock, and rotate infinitely.

Here's my question: how do I start off the input as one, and how do I make it so the reset signal doesn't affect how long the subsequent leds light up? (alternate question- Am I going about this just so incorrectly that I should give up right now and do it differently?)

shifter code:

module shift_reg(
    input clk,
    input rst,
    output [7:0] led
    );

//connector wire between flipflops
wire [7:0] bitshift;

// creating the shifter out of d flipflops

//1st one
d_ff d_ff0(
    .clk(clk),
    .rst(rst),
    .D(bitshift[0]),
    .Q(bitshift[1])
);

//middle ones
genvar i;
generate
for (i=1; i<7; i=i+1)
begin : d_ff_gen_label0
    d_ff d_ff_inst1(
        .clk(clk),
        .rst(rst),
        .D(bitshift[i]),
        .Q(bitshift[i+1])
    );
    end
endgenerate;

//last one
d_ff d_ff1(
    .clk(clk),
    .rst(rst),
    .D(bitshift[7]),
    .Q(bitshift[0])
);

assign led = bitshift;

endmodule

d flip-flop code:

module d_ff(
    input D,
    input clk,
    input rst,
    output reg Q
    );
always @(posedge (clk), posedge (rst))
begin
    if (rst == 1)
        Q <=1'b0;
    else
        Q <= D;
end
endmodule

One solution would be to have one of the FFs reset to 1 instead of 0.

To make your cycles of equal length, use a synchronous reset (instead of an asynchronous one, like you implemented)

For example:

module d_ff_high(
    input D,
    input clk,
    input rst,
    output reg Q
    );
always @(posedge clk)
begin
    if (rst == 1)  //only reset on a clock edge!
        Q <=1'b1;
    else
        Q <= D;
end
endmodule

...
//1st one
d_ff_high d_ff0(
...