I am new to hardware design using System Verilog, so I'm trying to compile a very very simple file: a D Flip Flop. it consists of the following code (taken from https://www.chipverify.com/verilog/verilog-modules):
//examples of module declaration
//here i will make a very simple d flip flop
//declaring a new component that will contain some logic
module dff(input d, input clk, input rstn, output reg q);
always @ (posedge clk)
begin
if(!rstn)
q <= 0;
else
q <= d;
end
endmodule
Whenever I go to compile I get the error
Error (12007): Top-level design entity "basics_of_verilog" is undefined
This makes sense. As my module "DFF" is named completely differently from the top level entity I declared at project creation.
However, I cannot set DFF to be the new top level entity. As the button to actually do it is greyed out. (https://i.sstatic.net/aFfC1.png)
I have never seen this before, can someone tell me what exactly is going on here? I've been scratching my head at this for a few minutes.
I already tried googling the error, but it seems that I'm the first person in recorded human history to encounter this error (I should get a nobel prize for this).
I found the solution.
For some reason, the option to make a current design file the top level hierarchy by selecting project > "Set as Top-Level Entity" is unavailable at times.
I got around this by doing the following: go into the project navigator window, then select the "hierarchy" drop down box. https://snipboard.io/2CyP4r.jpg then, right click on the file you wanna set as the top level hierarchy and select "Set as Top-Level Entity" https://snipboard.io/4kLheM.jpg
This fixed it. Props to Tushar for providing this solution!
