I have an FPGA project with multiple VHDL files (all compile with no errors), written in Lattice's Diamond software. The problem is when I go to assign pins all I see is the inputs and outputs of one VHDL file. If I delete that file, I see another, the netlist analyzer has the same behavior.
Is it possible to have multiple VHDL files within the same project or must I write everything in one VHDL file?
A hardware description language describes a design hierarchy. Each design unit, component or module is stored in a separate HDL file. In your case in different VHDL files. The top most VHDL design unit (entity) is called the top-level of your hierarchy. Only that file's ports can be assigned to device pins. All other ports of subordinate design units must be assigned by port maps in instantiations.
It's not a fault nor error of your tool. You should again about building design hierarchies and how to instantiate entities or components.