In VHDL does a signal passing through a port incur a delta cycle delay?

I know that in VHDL signal assignments incur a delta-cycle of delay, meaning that if I have:

bar <= foo;

bar will update one delta cycle after foo changes. But what about port connections? I know from experience that a signal passing through a port connection does not incur a delta-cycle delay, but I cannot explain why or justify it from the VHDL spec. In the VHDL-2008 spec section "6.5.6.3 Port clauses" it says "A port is itself a signal..." and then goes on to say:

If the actual part of a given association element for a formal port of a block ... is an expression that is not globally static, then the given association element is equivalent to association of the port with an anonymous signal implicitly declared in the declarative region that immediately encloses the block. ... [It] is the target of an implicit concurrent signal assignment statement of the form

anonymous <= E;

where E is the expression in the actual part of the given association element. The concurrent signal assignment statement occurs in the same statement part as the block.

All of this seems to imply that port connections are effectively signal assignments, so I would expect them to incur delta-cycle delays. I assume I am missing some critical part of the spec that explains this, but where is it? Specific references in the VHDL spec are appreciated.

The primary motivation for my question is to understand how clock distribution within a VHDL hierarchy does not create many different versions of the same clock, with different delta-cycle delays depending on the level in the hierarchy.

With VHDL-2008 and beyond, for input ports that have an expression that is not a type conversion (language defined conversion - what many other languages call a type cast) or type conversion function (a function with one parameter), the expression is replaced by a signal being assigned the expression and then the signal is connected to the input port. So this does result in a simulation cycle (aka delta cycle) delay.

All other port associations do not incur a simulation cycle delay.

entity e is
end entity e ;
architecture a of e is 
  . . . 
begin

  DUT_1 : DUT
    port map (
      A_unsigned => unsigned(In1_slv),      -- no delta delay
      B_unsigned => In2a_unsigned + 1,      -- has delta delay
      . . . 

For In1_slv, there is not delta delay as this is a type conversion, however, the expression, In2a_unsigned +1 is an expression on the input, hence, the simulator treats this the same as the following:

entity e is
end entity e ;
architecture a of e is 
  . . . 
begin

  In2a_plus_one <= In2a_unsigned + 1 ; 

  DUT_1 : DUT
    port map (
      A_unsigned => unsigned(In1_slv),      -- no delta delay
      B_unsigned => In2a_plus_one,          
      . . . 

Interesting brain teaser - and yes at least some synthesis tools allow the second one without an issue.

  DUT_1 : DUT
    port map (
      A_unsigned => not In1,      -- has delta delay
      B_unsigned => "not"(In1),   -- no delta delay, is a type conversion function   
      . . .