instantiating generic package in VHDL with a few constraints

I want to instantiante a generic package so that it's visible to an entity such that

• a generic to the entity is passed as a generic to the package
• one of the port types of the entity is defined in the package.

Question: Where/how to instantiate package, is it even possible? Below is a toy example of what I want:

package my_pkg is
    generic(
        my_param : postive
    );
    type my_type is array(0 to my_param - 1) of std_logic_vector(8-1 downto 0);
end my_pkg;

entity my_entity is
    generic(
        my_param_val : positive -- pass to package
    );
    port(
        my_input : my_type -- defined in package
    );
end entity my_entity;

-- where can I put this?
package my_pkg_inst is new work.my_pkg generic map (my_param => my_param_val);
use my_pkg_inst.all;

If I put the instantiation in the entity architecture, the port can't see my_type, and if I put the instantiation outside the entity, it can't see my_param_val.

Since VHDL 2008, you can also have packages as part of your generics, so I think what you want is a generic mapped package:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package my_pkg is
    generic(
        my_param : positive
    );
    type my_type is array(0 to my_param - 1) of std_logic_vector(8-1 downto 0);
end my_pkg;

entity my_entity is
    generic(
        my_param_val : positive;
        package my_pkg_generic is new work.my_pkg generic map (
            my_param => my_param_val
        )
    );
    port(
        my_input : my_pkg_generic.my_type -- defined in package
    );
end entity my_entity;

I'm not sure how well the tools support this syntax, but my editor is not complaining and it compiles fine using nvc