vhdl

vhdl can't determine type of object

The code below produces -

Error (10327): VHDL error at XXXX.vhd(1581): can't determine definition of operator ""&"" -- found 47 possible definitions Error (10647): VHDL type inferencing error at XXXX.vhd(1581): type of expression is ambiguous - "std_logic_vector" or "slvn_array" are two possible matches Error (10411): VHDL Type Conversion error at XXXX.vhd(1581): can't determine type of object or expression near text or symbol "UNSIGNED"

----CODE
usb_hid_phy_offload_address         <= std_logic_vector(unsigned(ENDPOINT0_CTRL_REG) + unsigned((("00000") & (cfg_hid_ep(v_selp)(5 downto 0)) & ("00"))));
---END CODE

I have tried every combination I can think of. Any suggestions are welcomed.

constant g_num_usbs  : integer range 1 to 8 := 2 ;
type     slvn_array is array (natural range <>) of  std_logic_vector ;

signal usb_hid_phy_offload_address : std_logic_vector(12 downto 0) ;
constant ENDPOINT0_CTRL_REG        : std_logic_vector(12 downto 0) := '0' & x"040" ;
signal cfg_hid_ep : slvn_array(g_num_usbs-1 downto 0)( 7 downto 0)  ;
Solution

  • Assuming my edit is correct and you renamed the type nios_reg_array to slvn_array.

    VHDL implicitly defines '&' for all single dimensional arrays. Hence concatenate is defined for:

      "&" [STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return SLVN_ARRAY]
  "&" [STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]

    Some simulators give better messages than others. The above is from nvc, an open source simulator - kudos to Nick G.

    The following uses the "&" defined for type unsigned instead of std_logic_vector and will work. Note I moved where unsigned was applied to be just around the std_logic_vector part of the array and left the concatenation outside of it.

    usb_hid_phy_offload_address <= 
    std_logic_vector(unsigned(ENDPOINT0_CTRL_REG) + 
    ("00000" & unsigned(cfg_hid_ep(v_selp)(5 downto 0)) & "00"));

    Since the length of ENDPOINT0_CTRL_REG matches that of usb_hid_phy_offload_address, there is no need for the extra "00000" in the concatenation and it will simplify to:

    usb_hid_phy_offload_address <= 
    std_logic_vector(unsigned(ENDPOINT0_CTRL_REG) + 
    (unsigned(cfg_hid_ep(v_selp)(5 downto 0)) & "00"));

    Knowing what signatures that caused the issue, you can also avoid the issue by concatenating with std_logic rather than std_logic_vector:

        usb_hid_phy_offload_address <= 
        std_logic_vector(unsigned(ENDPOINT0_CTRL_REG) + 
        unsigned((cfg_hid_ep(v_selp)(5 downto 0)) & '0' & '0') );

    All of the above compile.