VHDL Copying contents from one array of unsigned vector to another

For a convolution implementation in VHDL,

I am trying to copy the input port array_i (is of type array(7 downto 0) of unsigned(3 downto 0)) to another signal called padded_array_s (is of type array(9 downto 0) of unsigned(3 downto 0)) with the first and last elements of padded_array_s being 0.

So I wrote a basic code (inside a process) like this :

padded_array_s <= (others=>(others=>'0'));
    for ii in 7 downto 0 loop
      padded_array_s(ii+1) <= array_i(ii);
      report "Padded Array=" & integer'image(to_integer((padded_array_s(ii + 1))));
      report "ii=" & integer'image(ii);
    end loop;

However the contents of padded_array_s is always 0. I can see in the console that the value of array_i is non-zero.

I also know that the process runs. The issue seems to be specifically in the assignment statement.

I am not sure why since this is just basic assignment and both the sides have same type (unsigned(3 downto 0)).

I tried converting the right hand side of the assignment inside the loop to integer and then back to unsigned vector. I also tried playing around with the RESIZE function. Nothing seems to work.

Any suggestions would be welcome.

Thank you.

Have you tried:

padded_array_s <= "0000" & array_i & "0000" ;

"&" is implicitly supported for all single dimensional arrays - including arrays of arrays.

To print after a signal assignment, you need to wait at least a simulation cycle (aka delta cycle) for the output to update. Assuming the above is a concurrent assignment (not in a process), you could then print (with report) in a separate process:

PrintItProc : process 
begin
  -- signals have a simulation (aka delta) cycle delay on them
  wait on padded_array_s ; 

  for ii in 9 downto 0 loop
    report "Padded Array=" & to_hstring(padded_array_s(ii)) & "  ii = " & to_string(ii) ; 
  end loop;
end process PrintItProc ; 

If you wanted to print the value as an integer, use to_string(to_integer(padded_array_s(ii)). integer'image is ok, but in VHDL-2008 it is intended to be replaced by to_string. By using a wait on padded_array_s rather than a sensitivity list, you can make it so that there is no printing at time 0 sim cycle 0.

If you just want to fix your original process, you can do:

SomeProc : process
begin
    wait on array_i ; 
    padded_array_s <= (others=>(others=>'0'));
    for ii in 7 downto 0 loop
      padded_array_s(ii+1) <= array_i(ii);
      -- stop one simulation cycle (aka delta cycle) to allow signal to update
      wait for 0 ns ; 
      report "Padded Array=" & integer'image(to_integer((padded_array_s(ii + 1))));
      report "ii=" & integer'image(ii);
    end loop;
end process SomeProc ;

Note since this process uses wait for 0 ns, the wait on array_i must be used rather than a sensitivity list.