Is it okay to use level-triggered registers on an FPGA?

I'm trying to make a single-cycle processor and I was planning on doing something like the following:

• Clock rising edge: Opcode is latched onto output of block memory (this must be on a rising edge), PC is incremented
• Clock level high: Decode signals are generated, registers are read, the ALU does its computation
• Clock falling edge: ALU output is stored into a register, PC gets updated if there's a jump
• Clock level low: Block memory starts reading the next opcode

I recently learned from this question that it's not recommended to use falling_edge. The solution there was to move writes to the rising edge, but I don't think that work for me. Would it be a bad idea to move everything from "clock falling edge" to "clock level low"? Instead of

process (CLK)
begin
    if falling_edge(CLK) then
        reg <= inputData;
    end if;
end process;

I would do

process (CLK)
begin
    if CLK = '0' then
        reg <= inputData;
    end if;
end process;

Relative to trying to use both clock edges it's probably not a bad idea, assuming you can somehow make your code work like that. In general though it's a bad approach because FPGAs are designed for standard synchronous logic so you may find yourself running out of resources unusually quickly or having a hard time with timing.

I'd suggest using a standard clock at 2x the rate of your 'single cycle' clock, and treating each pair of rising edges as if the first was the rising edge and the second as if it was the falling. If necessary, include another signal that toggles on each 2x clock so you can tell which edge of the single cycle clock is coming next.