VHDL Generic number concatenation of std_logic_vector

I have an array of std_logic_vectors. The length of the array and std_logic_vectors are variable based on generics. How can I concatenate all the std_logic_vectors in my array without knowing the exact number of elements in my array?

Here's an example of what I need where I hard code the number of elements in the array:

  constant NUM_ELEMENTS  : integer := 3;
  constant VECTOR_LENGTH : integer := 2

  type t_small_vectors is array (0 to NUM_ELEMENTS-1) of std_logic_vector(VECTOR_LENGTH-1 downto 0);
  signal small_vectors : t_small_vectors;

  signal large_vector : std_logic_vector(NUM_ELEMENTS*VECTOR_LENGTH-1 downto 0);

begin
 
  large_vector <= small_vectors(2) & small_vectors(1) & small_vectors(0);

end architecture 

This example doesn't work for me because I would need to change a line of code every time I changed NUM_ELEMENTS

I realize this has to fit in a generate statement or a for loop in a process but can't think through how it'd work.

This is basically a type conversion. For this you will need a loop. For a specific case, you could use a generate loop

Large_vector_gen: For I in NUM_ELEMENTS-1 downto 0 generate
  large_vector((i+1)*VECTOR_LENGTH-1 downto i*VECTOR_LENGTH) <= small_vectors(i);
End generate; 

But this is definitely something that could better be done in a function (this is vhdl2008)

Function to_long_vector( l : t_small_vectors ) return std_logic_vector is
  Constant VECTOR_LENGTH : natural l'element'length;

  Variable r : std_logic_vector(VECTOR_LENGTH*l'length-1 downto 0);
Begin
  For i in l'range loop
    R((i+1)*VECTOR_LENGTH-1 downto i*VECTOR_LENGTH) := l(i);
  End loop;

  return r;
End function;