What is this error 'Checker 'xor_module_b' not found. Instantiation 'x0_1' must be of a visible checker.'? I am writing verilog code in behavioral model by using module instantiation. While compiling i am getting the error. Portion of code and error is attached.
module CSSA4_4bit_modified_b(s,cin,g,G,GP,a,b);
input cin,g,G,GP;
input [7:0] a,b;
output wire [7:0] s;
wire [6:0] c0;
wire [3:0] c1;
wire [2:0] pro;
wire [7:0] s0;
wire [3:0] s1;
always@(a,b,cin,g,G,GP)
begin
//Subblock 1
//Sum bit 0
xor_module_b x0_1(.a(a[0]), .b(b[0]),.s0(s0[0]));
xor_module_b x0_2(.a(s0[0]),.b(cin), .s0(s[0]));
and_logic_b a0 (.a(s0[0]), .b(cin), .out(pro[0]));
//end
//Sum bit 1
FA_b FA_b1(.a(a[1]), .b(b[1]), .c(g),.sum(s0[1]),.cout(c0[0]));
xor_module_b x1 (.a(s0[1]),.b(pro[0]),.s0(s[1]));
and_logic_b a1 (.a(s0[1]),.b(pro[0]), .out(pro[1]));
//end
//Sum bit 2
FA_b FA_b2(.a(a[2]), .b(b[2]), .c(c0[0]),.sum(s0[2]),.cout(c0[1]));
xor_module_b x2 (.a(s0[2]),.b(pro[1]),.s0(s[2]));
and_logic_b a2 (.a(s0[2]),.b(pro[1]),.out(pro[2]));
//end.......continued
//Sum bit 7
FA_b FA_b1_7_1(.a(a[7]),.b(b[7]),.c(c0[5]), .sum(s0[7]),.cout(c0[6]));
FA_b FA_b1_7_2(.a(a[7]),.b(b[7]),.c(c1[2]), .sum(s1[3]),.cout(c1[3]));
sum_select_mux_b M1_7(.Sum(s[7]),.Sum0(s0[7]),.Sum1(s1[3]),.C8k(cin));
//End of subblock 2
//End of CSSA 4-4 bit
end
endmodule
You can not instance a module inside an always.
Remove the always@(a,b,cin,g,G,GP)
You don't need the always here but in case you DO need it:
Listing your variable in the always is dangerous. If you forget one you are likely to get mismatches between simulation and reality (gates). Better to let the compiler work it out by using: always @( * )
You can use it in test benches but I can't remember ever needing it.
