system-verilog-assertions

Is there a way to skip the first evaluation of an SVA?

I have the following property:

property p_0;
 $rose(signal_a) |-> $rose(signal_b) ;
endproperty

my problem is, after HW RST, signal_b rises (normal behavior) but the assertion fails, and I want this check to be evaluated only later.

I wanted to work with first_match() with something like below:

p_0_a : assert property ( ! first_match(p_0)) else `uvm_fatal(...)

so that I skip the first match of this property but the compiler generates a syntax error.

Is there a way to skip the evaluation of SVAs after specific number of iterations?

Solution

  • Cascaded implication operators may well help you out, for example something along the lines of:

    assert property (reset |-> p_0);

    Basically, |=> and |-> are right-associative:

    A |=> B |=> C

    means

    A |=> ( B |=> C )

    ie If A happens, check (B |=> C) immediately afterwards. If A does not happen, don't check (B |=> C).