I'm trying to make an SR flipflop on Icarus Verilog.
Flipflop module:
module srff(sr,clk,q,qb);
input [1:0]sr;
input clk;
output reg q,qb;
always@(posedge clk) begin
case(sr)
2'b00: q=q;
2'b01: q=0;
2'b10: q=1;
2'b11: q=1'bz;
endcase
end
assign qb=~q;
endmodule
Testbench:
module sr_ff_test;
reg [1:0]sr;
reg clk;
wire q,qbar;
srff sr_ff_test(sr,clk,q,qbar);
initial begin $dumpfile("dump1.vcd");
$dumpvars(0,sr_ff_test);
end
initial begin
$monitor("S=%d, R=%d, CLK=%d, Q=%d, Qbar=%d",sr[0],sr[1],clk,q,qbar);
sr[0]=1'b0;
sr[1]=1'b1;
clk=1;
#100
sr[0]=1'b0;
sr[1]=1'b1;
#100
sr[0]=1'b0;
sr[1]=1'b0;
#100
sr[0]=1'b1;
sr[1]=1'b1;
#100
sr[0]=1'b0;
sr[1]=1'b1;
#100
sr[0]=1'b0;
sr[1]=1'b1;
end
endmodule
The error is as given in the question (line 14 of testbench - the one with monitor...). What went wrong, and how do I fix this?
I'm new to Icarus Verilog, and I don't know if I have accidentally used commands that aren't usable.
The error is in the srff
module. You declared qb
as a reg
, but then you try to drive it with a continuous assignment using the assign
keyword.
The solution is to not declare it as a reg
. Change:
output reg q,qb;
to:
output reg q;
output qb;