verilogsystem-verilogsynthesis

Setting values in an initial block in Verilog

I think I may be mis-understanding how the initial block works in Verilog.

I have the following bit of code driving hardware sprites:

// horizontal and vertical screen position of letters
logic signed [CORDW-1:0]            spr_x[SPR_CNT];
logic signed [CORDW-1:0]            spr_y;

initial begin
    spr_x[0] = 20;
    spr_x[1] = spr_x[0] + 30;
    spr_x[2] = spr_x[1] + 30;
    spr_x[3] = spr_x[2] + 30;
    spr_x[4] = spr_x[3] + 30;
    
    spr_y = 100;

    ...
end

always_comb begin
    spr_y = 16'd100;

    spr_x[0] = 20;
    spr_x[1] = spr_x[0] + 30;
    spr_x[2] = spr_x[1] + 30;
    spr_x[3] = spr_x[2] + 30;
    //spr_x[4] = spr_x[3] + 30;

    ...
end

genvar m;  // for looping over sprite instances  
generate for (m = 0; m < SPR_CNT; m = m + 1) begin : sprite_gen
    sprite spr0 (
        .i_reset_n(i_reset_n),
        .i_clock(i_pixel_clock),
        .i_spr_y(spr_y),
        .i_spr_x(spr_x[m]),
    );
end endgenerate

I was under the impression that values assigned inside the initial block would stick because they are assigned to logic types which keep their values.

In the example above though my last sprite (index 4) does not display at the correct x position because the spr_x value is not refreshed in always_comb.

I'm surely missing or misunderstanding something here.

Solution