[SOLVED] Connecting output of 4-bit counter to Hex to 7-Seg decoder and creating testbench

Connecting output of 4-bit counter to Hex to 7-Seg decoder and creating testbench

I have the general abstract idea, but doing it in Verilog is very hard for me. I know I have to connect the two and then make a testbench. Would that require 2 more modules? I have trouble understanding how to declare inputs and outputs correctly, and that makes it hard to make the testbench.

The input of the counter is a clock, and the output is 4 bits. That 4 bit connects to the 4 bit input of the decoder. The testbench needs to display the clock input, 4 counter outputs, and the 7 outputs of the decoder.

One thing that is unclear is whether I need one more module to connect the two modules, or can I just implement this functionality into one testbench?

//4-bit counter counting from 0000 to 1111

module lab_x_counter (clk, cnt);

input clk;   
output reg[3:0] cnt;

always @(posedge clk) begin
cnt <= cnt + 1;
end

initial
cnt <= 0;
endmodule


//Hex to 7-seg
module lab_x_behavioral (SW, HEX0);

   input [3:0] SW;
   output [6:0] HEX0;  
  
   bcd_behavioral u0 (SW[3:0], HEX0[6:0]);
endmodule


module bcd_behavioral (bcd, HEX0);
input [3:0] bcd;
output reg [6:0] HEX0;

always @(bcd) begin
   case (bcd)

4'b0000: HEX0 <= ~7'b0111111;
4'b0001: HEX0 <= ~7'b0000110;
4'b0010: HEX0 <= ~7'b1011011;
4'b0011: HEX0 <= ~7'b1001111;
4'b0100: HEX0 <= ~7'b1100110;
4'b0101: HEX0 <= ~7'b1101101;
4'b0110: HEX0 <= ~7'b1111101;
4'b0111: HEX0 <= ~7'b0000111;
4'b1000: HEX0 <= ~7'b1111111;
4'b1001: HEX0 <= ~7'b1101111;

4'b1010: HEX0 <= ~7'b1110111;
4'b1011: HEX0 <= ~7'b1111100;
4'b1100: HEX0 <= ~7'b0111001;
4'b1101: HEX0 <= ~7'b1011110;
4'b1110: HEX0 <= ~7'b1111001;
4'b1111: HEX0 <= ~7'b1110001;
endcase
end
endmodule

Solution

Instead of your lab_x_behavioral module, I created a tb module without ports. Then I instantiated the counter, added a clock, and made the connections. There is no need for the port names to match. Here is one way to code a quick testbench:

module tb;
   wire [3:0] cnt;
   wire [6:0] HEX0;
   reg clk = 0;

   bcd_behavioral u0 (cnt, HEX0);
   lab_x_counter  u1 (clk, cnt);

always #5 clk = ~clk;

initial begin
     #500 $finish;
end
endmodule