Error opening .vcd file. No such file or directory

My Verilog code is stored in C:\FA. There are three files:

FA.v, fa.vvp, TM_FA.v

I followed my book steps.

1. iverilog -o fa.vvp
2. vvp fa.vvp
3. finish
4. getwave fa.vcd &

When I use getwave fa.vcd & to simulate it, and then it shows:

Error opening  .vcd file 'fa.vcd'.
Why: No such file or directory

I firstly use Icarus and GTKwave, then I don't know how to fix it.

You need to add code in your Verilog testbench to explicitly tell iverilog to create a VCD file. The iverilog documentation states:

// Do this in your test bench

initial
 begin
    $dumpfile("test.vcd");
    $dumpvars(0,test);
 end