system-veriloguvm

What's point of port to port type of connection in TLM?


In UVM TLM1, there are three main interface types:

Typically, to connect a port to an implementation through the component hierarchy, one would chain connections like this:

port → export → export → ... → export → imp

However, it is also possible to connect a port to another port. From my understanding, this seems similar to connecting a port to an export.

My question:

What is the reason for using a port-to-port connection instead of a port-to-export connection in UVM TLM1?


Solution

  • A port-to-port connection is analogous to an export-to-export connection as you ascend the component hierarchy. In this scenario, you connect a port in a lower-level component to a port in a higher-level component.

    For example, the analysis port of a driver might be connected to the analysis port of the containing agent. Imagine a port as a requirement for connection to an implementation, while an export serves as a provider of that implementation. It would not make sense for the agent to have an export since it doesn’t offer the implementation.