system-verilog

Connection using modports with different signals

Is it allowed to connect two modules using SV interface modports with different signals?

interface chip_bus ();
   logic [31 :0] address;
   logic [63:0]  data;
   logic [63:0]  req;
  // The two modports use different signals
  modport master (input  address, output req);
  modport slave  (output address, input  data);
endinterface

// primary
module primary   (chip_bus.master pins); 
endmodule

// secondary
module secondary (chip_bus.slave pins);
endmodule

// top
module top ();
   chip_bus  bus  (); 
   secondary i2   (bus) ;
   primary   il   (bus); 
endmodule
Solution

  • A modport is a portmanteau or blend of module and port, serving as a placeholder for what you would have written without the availability of the interface port construct.

    Essentially, you are describing the primary module as having an input port address and an output port req, while the secondary module has an output port address and an input port data. You are correct in saying that the only shared signal between the two modules is the address connection.