Signals not going forward from initial state in Verilog test bench

I am working with a system of two d_flipflops (DFFs) connected to each other (with output,q, of first DFF connected to input,d, of second flipflops. I created sub-modules of DFFs and embedded them into a top module. I then created a test bench. However the problem is that the simulation doesn't progress beyond the initial state irrespective of the time-delays I provide. It says simulation is finished at t=0. while there is no error in compilation, I dont understand whats wrong with my code. I also tried providing absolute time values as delays in test bench (e.g #50ns instead of #50) but of no use. I tried simulating this in iverilog and also tried different compilers from EDAplayground. It would be of great help to me if someone could provide insights to my problem. Thank you!

module d_ff(d, clk, reset, q, q_not);

input d, clk, reset;

output q, q_not;

reg q, q_not;



always @ (reset or posedge clk)
begin
	if (reset == 0)
	begin
		q<=d;
		
		q_not <= ~d;
	end
	else 
	begin 
		q<=1'b0;
		
		q_not <= 1'b1;	
	end

end


endmodule




module main(d, clk, reset, q2, q2_not, q1_not);

input d, clk, reset;

output q2, q2_not, q1_not;


wire d2;

d_ff dup(.d(d), .clk(clk), .reset(reset), .q(d2), .q_not(q1_not));
d_ff dup2(.d(d2), .clk(clk), .reset(reset), .q(q2), .q_not(q2_not));



initial
begin
$display("end of main module");
$finish;
end

endmodule

Here is the testbench:

// Code your testbench here
// or browse Examples
`timescale 1 ns / 100 ps /// 100ps


module main_tb;


reg d, clk, reset;

wire q2, q2_not, q1_not;


main UUT(.d(d), .clk(clk), .reset(reset), .q2(q2), .q2_not(q2_not), .q1_not(q1_not));


initial
begin

clk = 0;
d=1'b0;
reset=1'b1;
#500ns reset=1'b0;

end

always begin
#50ns clk = !clk;

end


initial
begin
  $dumpfile("dump.vcd");
$dumpvars;
end


initial
begin
$monitor("clk = %b, d=%b, reset=%b, q=%b, q_not=%b, d2_not=%b", clk,d,reset, q2,q2_not, q1_not);


#500 reset =1'b1;
#500 d=1'b1;
#500 reset =1'b0;
#500 d=1'b0;
#500 reset = 1'b0;
#500 d=1'b0;
#500 reset = 1'b0;
#500 d=1'b0;
#500 d=1'b1;
#100 reset =1'b1;
#500 d = 1'b1;
 
#50000ns $finish;
end

endmodule

This:

initial
begin
   $display("end of main module");
   $finish;
end

Is killing your simulation as all initial statements are run in parallel. Remove it and put a $finish or $stop at the end of the main initial.
Also better to move all clk assignment into the clk block, the same with reset and b:

initial
begin
   clk = 1'b0;
   forever 
      #50ns clk = !clk;
end


initial
begin
   $monitor("clk = %b, d=%b, reset=%b, q=%b, q_not=%b, d2_not=%b", clk,d,reset, q2,q2_not, q1_not);
   d=1'b0;
   reset=1'b1;
   #500ns reset=1'b0;
   #500 reset =1'b1;
   #500 d=1'b1;
   #500 reset =1'b0;
   #500 d=1'b0;
   ...
   $finish; // $stop;
end