How to have a signal which has specific delay after clock positive edge?

I have a testbench module such as below:

`timescale 1ns / 1ps
module RandomDelay_tb;
    reg t_clk=1;
    reg t_rst_n=1;
    reg t_input_signal = 1;
    wire t_out_signal;
    MyModle r1 (t_clk,t_rst_n,2'b11,t_input_signal,t_out_signal);
    initial
    begin
            t_rst_n = 0;
            #930 t_rst_n = 1;
    end
    
    always
        #100 t_clk = ~t_clk;
    always
        #50  t_input_signal = ~ t_input_signal;
endmodule
 

In this module, the frequency of t_input_signal is twice that of t_clk. I want to modify it such that it has a toggle period the same as t_clk, i.e., 100ns, but it has a delay after the edge of my clock signal like 10ns.

In other words, I want t_input_signal to be t_clk but shifted for 10ns.

How can I implement such a thing?

There are several ways, but looking at your code, the least amount of typing would be:

always @(t_clk)
   t_input_signal <= #10 t_clk;