verilogvivado

Design with MicroBlaze has more instantiated block-RAMs than device capacity. Consider targetting to a different part


I have a design which is using the Xilinx part: XC7A100T (FGG484ABX21), the environment: WIN10 19043.1348, VIVADO 2018.3. According to the datasheet: https://www.xilinx.com/content/dam/xilinx/support/documentation/selection-guides/cost-optimized-product-selection-guide.pdf#A7, XC7A100T should have 4,860 Kb (4860*1000/8/1024=593 KiB) BRAM, and I am using only 512 KiB of them.

The Memory Address Assignment is as follows: enter image description here

VIVADO throws me the error when I try to do the synthesis: enter image description here

What could be wrong? Thank you!


Solution

  • :) Thanks man @Pradyuman Bissa. Problem resolved. The GPIB FIFO uses nearly 50% of the BRAMs.