Testing multiple configurations of parameterizable modules in a Verilog testbench

Say I have a Verilog module that's parameterizable like the below example:

// Crunches numbers using lots of parallel cores
module number_cruncher
    #(parameter NUMBER_OF_PARALLEL_CORES = 4)
    (input clock, ..., input [31:0] data, ... etc);
    // Math happens here
endmodule

Using Verilog 1364-2005, I want to write a testbench that runs tests on this module with many different values NUMBER_OF_PARALLEL_CORES.

One option that I know will work is to use a generate block to create a bunch of different number_crunchers with different values for NUMBER_OF_PARALLEL_CORES. This isn't very flexible, though - the values need to be chosen at compile time.

Of course, I could also explicitly instantiate a lot of different modules, but that is time consuming and won't work for the sort of "fuzz" testing I want to do.

My questions:

• Is there a way to do this by using a plusarg passed in from the command line using $value$plusargs? (I strongly suspect the answer is 'no' for Verilog 1364-2005).
• Is there another way to "fuzz" module parameterizations in a testbench, or is using a generate block the only way?

Since $value$plusargs is evaluated at runtime, it can not be used to set parameter values, which must be done at compile-time.

However, if you use generate to instantiate multiple instances of the design with different parameter settings, you might be able to use $value$plusargs to selectively activate or enable one instance at a time. For example, in the testbench, you could use the runtime argument to only drive the inputs of a specific instance.