verilogsimulationsystem-verilogvivadotest-bench

Testbench issue for glowing/fading LED not producing a waveform

I was working through a nice tutorial for a simple glowing LED design from fgpa4fun.com, but I can't get the testbench to output a waveform for the LED (it just stays at value X).

I'm using a Zybo Z7 board with clock 125MHz.

Below is the module:

`timescale 1ns / 1ps

module LED_Glow(i_Clk, o_LED);
input i_Clk;
output o_LED;

// Clock frequency 125MHz, glow frequency 1Hz -> count up to 125MHz
reg [26:0] r_Count;
wire [5:0] w_Intensity = r_Count[26] ? r_Count[25:20] : ~r_Count[25:20];
reg [6:0] r_PWM;

always @(posedge i_Clk)
    begin
        r_Count <= r_Count + 1;
        r_PWM <= r_PWM[5:0] + w_Intensity;
    end

assign o_LED = r_PWM[6];
    
endmodule

and this is my testbench:

`timescale 1ns / 1ps

module tb_LED_Glow();

reg r_Clk;
wire w_LED;

LED_Glow one(.i_Clk(r_Clk), .o_LED(w_LED));

initial
    begin
        $monitor("r_Clk=%b, w_LED=%b",r_Clk, w_LED);
        r_Clk <= 1'b0;
    end
    
always #1 r_Clk <= ~r_Clk;

endmodule

I am able to synthesize, implement and program my device fine, and the LED glows as expected, but the simulated waveform looks like this, and I'm not sure why:

Waveform

Solution

  • The problem is in the design module (LED_Glow), not in the testbench module (tb_LED_Glow).

    The default value for reg types is x (unknown). You declared r_Count as reg, which means it has the value of x at simulation time 0. At the 1st posedge of i_Clk, adding 1 to r_Count has no effect; r_Count remains x. r_Count remains x for the duration of the simulation.

    The same is true of the r_PWM signal.

    You need to initialize these signals with known values. One way to do so is as follows:

    reg [26:0] r_Count = 0;
reg [6:0] r_PWM = 0;

    waves