Continuous Assignment of Class Property

Title says it all. I'm wondering if there is a way to continuously assign a class property in SystemVerilog.

Something along the lines of:

class test;
    logic test_var [2];
    logic foo; 
 
    function new(); 
        this.foo         = '0; 
        this.test_var[0] = '0;
        assign this.test_var[1] = foo; // continous assignment, however that is possible 
    endfunction

    task updateFoo(input logic temp_foo);
        this.foo = temp_foo; 
    endtask 

    task readTestVar(); 
        $display("%b and %b", this.test_var[0], this.test_var[1]); 
    endtask

endclass

initial begin
    test ex = new();  // Foo and test_var initialize to zero. 
    ex.readTestVar(); // Prints "0 and 0" 
    ex.updateFoo(1);  // Foo becomes 1, so does test_var[1]
    ex.readTestVar();  // Prints "0 and 1"
end 

I've searched some testbooks and the internet, but haven't found anything useful. I suppose I know how to solve this the long way around, but wondering if there is a short way.

When using classes, you have to fork your own process. You cannot use always or continuous assignments.

module top;
  class test;
    logic test_var [2];
    logic foo; 
 
    function new(); 
      this.foo         = '0;
      this.test_var[1] = '0;
      fork
        forever @foo this.test_var[1] = foo; // continous assignment
      join_none
    endfunction

    function void updateFoo(input logic temp_foo); // Dont use tasks unless they need to consume time
        this.foo = temp_foo; 
    endfunction

    function void readTestVar(); 
        $display("%b and %b", this.test_var[0], this.test_var[1]); 
    endfunction

endclass

test ex; // static variable declaration moved outside of procedural block
initial begin // delays added to prevent race conditions. 
    ex = new();  // Foo and test_var initialize to zero.
    #1 ex.readTestVar(); // Prints "0 and 0" 
    #1 ex.updateFoo(1);  // Foo becomes 1, so does test_var[1]
    #1 ex.readTestVar();  // Prints "0 and 1"
end 
endmodule