vhdlsynthesizer

Index value 0 to 8 could be out of prefix range 1 to 8 - VHDL

In my code I'm defining this vector:

Data: in std_logic_vector(1 to 8);

So I have an input 0:7 and I solve a counter problem when it reaches 0. But my Synthesizer gives me this warning:

Index value 0 to 8 could be out of prefix range 1 to 8

It can create errors? Or it just warns that if I use index 0, it can create errors?

Solution

  • It looks like you are indexing your vector with a value that has 9 values in its range (such as signal index : integer range 0 to 8), but your vector only has 8 values (so you need signal index : integer range 1 to 8). If you post the code where you use in, and the declarations for any signals/values involved in indexing, we can provide more details.