Increasing the speed of Xilinx ISim simulation

I have a large ISim design for Spartan-6 using about 6 of the Spartan-6 FPGA IP cores. It needs to run for a simulation time of 13 seconds, but at present takes 40 seconds to run a simulation time of 1 ms. During the 13 seconds it will also write 480000 24 bit std_logic_vectors to a text file.

This equates to running time of 144 hours to run the entire simulation (almost a week!).

Is there a way, for example, of increasing the step size or turning off the settings for waveform plotting etc, or any other settings I can use to increase the simulation speed?

So far I have tried not plotting the waveform, but it doesn't seem to actually increase the speed.

Thanks very much

Yes adding signals to the waveform slowes every simulator down... but running such long simulations always create GiB of data and take hours or days.

You could check your code and:

• improve sensitivity lists to reduce calculation cycles
• some IP cores have a fast simulation mode which can be enabled by a generic parameter.

But in general there is only one solution: use another simulator. Especially one with optimization. (Can be disabled or restricted in free editions) E.g.:

• GHDL - is open source and quite fast
• QuestaSim / ModelSim
  ModelSim is for example included in Altera Quartus Prime (WebPack) for free as Starter Edition.
• Active-HDL
  Active-HDL Student Edition is free to use. Alteratively, it's included in Lattice Diamond.

P.S. 40 sec for 1 ms (25 us per second) is very fast. My integration simulations usually calculate 20 ns per second. So you are 1000x faster)