Structural design of Shift Register in VHDL
I've made a structural design of a shift register in vhdl . When WriteShift is 1 then I got shift and when it is 0 then shift register loads a price. Although load works perfectly when I set writeshift to 1 in testbench I get 00000 in simulation.
My code is the following:
entity ShiftRegis is
Port ( Din : in STD_LOGIC_VECTOR (4 downto 0);
WriteShift : in STD_LOGIC;
Clock : in STD_LOGIC;
reset : in STD_LOGIC;
En : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (4 downto 0));
end ShiftRegis;
architecture Behavioral of ShiftRegis is
component notGate
Port ( in0 : in STD_LOGIC;
out0 : out STD_LOGIC);
end component;
component nand4Gate
Port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3 : in STD_LOGIC;
bitOut : out STD_LOGIC);
end component;
component D_FlipFlop
Port ( Din : in STD_LOGIC;
En : in STD_LOGIC;
Q : out STD_LOGIC;
reset : in STD_LOGIC;
Clk : in STD_LOGIC);
end component;
signal q4, q3, q2, q1, in3, in2, in1, in0, notWS : std_logic;
begin
ff4 : D_FlipFlop
port map( Din => Din(4),
En => En,
Q => q4,
reset => reset,
Clk => Clock);
ff3 : D_FlipFlop
port map( Din => in3,
En => En,
Q => q3,
reset => reset,
Clk => Clock);
ff2 : D_FlipFlop
port map( Din => in2,
En => En,
Q => q2,
reset => reset,
Clk => Clock);
ff1 : D_FlipFlop
port map( Din => in1,
En => En,
Q => q1,
reset => reset,
Clk => Clock);
ff0 : D_FlipFlop
port map( Din => in0,
En => En,
Q => Q(0),
reset => reset,
Clk => Clock);
notg4 : notGate
port map( in0 => WriteShift,
out0 => notWS);
nandg3 : nand4Gate
port map( i0 => Din(3),
i1 => notWS,
i2 => WriteShift,
i3 => q4,
bitOut => in3);
nandg2 : nand4Gate
port map( i0 => Din(2),
i1 => notWS,
i2 => WriteShift,
i3 => q3,
bitOut => in2);
nandg1 : nand4Gate
port map( i0 => Din(1),
i1 => notWS,
i2 => WriteShift,
i3 => q2,
bitOut => in1);
nandg0 : nand4Gate
port map( i0 => Din(0),
i1 => notWS,
i2 => WriteShift,
i3 => q1,
bitOut => in0);
Q(4) <= q4;
Q(3) <= q3;
Q(2) <= q2;
Q(1) <= q1;
end Behavioral;
Solution
Your load (WriteShift = '1' and en = '1') doesn't work either.
There's a design flaw where you're using 4 input NAND gates where you need a 2:1 Multiplexer for selecting between Din and q bits for the four LSBs in the shift register.
That's fixed by creating 2:1 muxes using three 2 input NOR gates:
architecture behavioral of shiftregis is
component notgate
port (
in0: in std_logic;
out0: out std_logic
);
end component;
-- component nand4gate
-- port (
-- i0: in std_logic;
-- i1: in std_logic;
-- i2: in std_logic;
-- i3: in std_logic;
-- bitout: out std_logic
-- );
-- end component;
component nor2gate
port (
i0: in std_logic;
i1: in std_logic;
bitout: out std_logic
);
end component;
component d_flipflop
port (
din: in std_logic;
en: in std_logic;
q: out std_logic;
reset: in std_logic;
clk: in std_logic
);
end component;
signal q4, q3, q2, q1, in3, in2, in1, in0, notws: std_logic;
signal nor2g0a, nor2g0b: std_logic; -- ADDED
signal nor2g1a, nor2g1b: std_logic; -- ADDED
signal nor2g2a, nor2g2b: std_logic; -- ADDED
signal nor2g3a, nor2g3b: std_logic; -- ADDED
begin
ff4:
d_flipflop
port map (
din => din(4),
en => en,
q => q4,
reset => reset,
clk => clock
);
ff3:
d_flipflop
port map (
din => in3,
en => en,
q => q3,
reset => reset,
clk => clock
);
ff2:
d_flipflop
port map (
din => in2,
en => en,
q => q2,
reset => reset,
clk => clock
);
ff1:
d_flipflop
port map (
din => in1,
en => en,
q => q1,
reset => reset,
clk => clock
);
ff0:
d_flipflop
port map (
din => in0,
en => en,
q => q(0),
reset => reset,
clk => clock
);
notg4:
notgate
port map (
in0 => writeshift,
out0 => notws
);
-- norg3:
-- nand4gate
-- port map (
-- i0 => din(3),
-- i1 => notws,
-- i2 => writeshift,
-- i3 => q4,
-- bitout => in3
-- );
norg3a:
nor2gate
port map (
i0 => din(3),
i1 => writeshift,
bitout => nor2g3a
);
norg3b:
nor2gate
port map (
i0 => notws,
i1 => q4,
bitout => nor2g3b
);
nor3gc:
nor2gate
port map (
i0 => nor2g3a,
i1 => nor2g3b,
bitout => in3
);
-- norg2:
-- nand4gate
-- port map (
-- i0 => din(2),
-- i1 => notws,
-- i2 => writeshift,
-- i3 => q3,
-- bitout => in2
-- );
norg2a:
nor2gate
port map (
i0 => din(2),
i1 => writeshift,
bitout => nor2g2a
);
norg2b:
nor2gate
port map (
i0 => notws,
i1 => q3,
bitout => nor2g2b
);
nor2gc:
nor2gate
port map (
i0 => nor2g2a,
i1 => nor2g2b,
bitout => in2
);
-- norg1:
-- nand4gate
-- port map (
-- i0 => din(1),
-- i1 => notws,
-- i2 => writeshift,
-- i3 => q2,
-- bitout => in1
-- );
norg1a:
nor2gate
port map (
i0 => din(1),
i1 => writeshift,
bitout => nor2g1a
);
norg1b:
nor2gate
port map (
i0 => notws,
i1 => q2,
bitout => nor2g1b
);
nor1gc:
nor2gate
port map (
i0 => nor2g1a,
i1 => nor2g1b,
bitout => in1
);
-- norg0:
-- nand4gate
-- port map (
-- i0 => din(0),
-- i1 => notws,
-- i2 => writeshift,
-- i3 => q1,
-- bitout => in0
-- );
norg0a:
nor2gate
port map (
i0 => din(0),
i1 => writeshift,
bitout => nor2g0a
);
norg0b:
nor2gate
port map (
i0 => notws,
i1 => q1,
bitout => nor2g0b
);
nor0gc:
nor2gate
port map (
i0 => nor2g0a,
i1 => nor2g0b,
bitout => in0
);
q(4) <= q4;
q(3) <= q3;
q(2) <= q2;
q(1) <= q1;
end architecture behavioral;
And that gives:
Where you see on q(0) that between A and B a '0' is output, B and C a '1, C and D a '0', D and E a '1' and E and F a '1', following that the shifted in values for Din(4), because there's no mux on the din input to ff4.
You'll notice the LSB goes out first.
Repetitively instantiated components can in general be a target for the use of generate statements.
Without a Minimal, Complete, and Verifiable example I had to guess and settled on an asynchronous reset for the D_flipflop component.
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