vhdlxilinx-isespartan

Displaying different numbers on 2 seven segment displays on VHDL (Spartan 3)


We have an assignment about decoding. 4 input switches (binary combination) and displays the corresponding switch combination to 4-LED and decimal value to 1 seven-segment. And convert those binary combination to Grey Code (4 bit also) and display corresponding 4-LED and decimal value to 1 seven-segment.

I already have the solution for the K-Mapping, but my main problem is to print different numbers on both segments. My problem is that it displays the last parsed code. They have the same output to the seven segment.

Here is my code..

entity BinaryToGrey is
    Port ( Bin : in  STD_LOGIC_VECTOR (3 downto 0);
              BinLed: out STD_LOGIC_VECTOR (3 downto 0);
              Enable: in STD_LOGIC_VECTOR (3 downto 0);
              Segment: out STD_LOGIC_VECTOR (6 downto 0);
           Grey : inout  STD_LOGIC_VECTOR (3 downto 0));
end BinaryToGrey;

architecture Behavioral of BinaryToGrey is

begin

Grey(3) <= Bin(3);
Grey(2) <= Bin(3) XOR Bin(2);
Grey(1) <= Bin(2) XOR Bin(1);
Grey(0) <= Bin(1) XOR Bin(0);

    process(Bin)

begin
case Bin is
when "0000"=> BinLed <="0000";  -- '0'
        when "0001"=> BinLed <="0001";  -- '1'
        when "0010"=> BinLed <="0010";  -- '2'
        when "0011"=> BinLed <="0011";  -- '3'
        when "0100"=> BinLed <="0100";  -- '4' 
        when "0101"=> BinLed <="0101";  -- '5'
        when "0110"=> BinLed <="0110";  -- '6'
        when "0111"=> BinLed <="0111";  -- '7'
        when "1000"=> BinLed <="1000";  -- '8'
        when "1001"=> BinLed <="1001";  -- '9'
        when "1010"=> BinLed <="1010";  -- 'A'
        when "1011"=> BinLed <="1011";  -- 'b'
        when "1100"=> BinLed <="1100";  -- 'C'
        when "1101"=> BinLed <="1101";  -- 'd'
        when "1110"=> BinLed <="1110";  -- 'E'
        when others => BinLed <="1111"; -- 'F'
    end case;
    end process;


process(Bin,Enable)
begin
        Enable(0) = '0';
        Enable(1) = '1';
        Enable(2) = '1';
        Enable(3) = '0';
        case Bin is 
        when "0000"=> Segment <="1111110";  -- '0'
        when "0001"=> Segment <="0110000";  -- '1'
        when "0010"=> Segment <="1101101";  -- '2'
        when "0011"=> Segment <="1111001";  -- '3'
        when "0100"=> Segment <="0110011";  -- '4' 
        when "0101"=> Segment <="1011011";  -- '5'
        when "0110"=> Segment <="1011111";  -- '6'
        when "0111"=> Segment <="1110000";  -- '7'
        when "1000"=> Segment <="1111111";  -- '8'
        when "1001"=> Segment <="1111011";  -- '9'
        when "1010"=> Segment <="1110111";  -- 'A'
        when "1011"=> Segment <="0011111";  -- 'b'
        when "1100"=> Segment <="1001110";  -- 'C'
        when "1101"=> Segment <="0111101";  -- 'd'
        when "1110"=> Segment <="1001111";  -- 'E'
        when others => Segment <="1001011"; -- 'F'
    end case;

end process;


process(Grey,Enable)
begin

    Enable(0) = '0';
    Enable(1) = '1';
    Enable(2) = '1';
    Enable(3) = '0';
    case Grey is 
        when "0000"=> Segment <="1111110";  -- '0'
        when "0001"=> Segment <="0110000";  -- '1'
        when "0010"=> Segment <="1101101";  -- '2'
        when "0011"=> Segment <="1111001";  -- '3'
        when "0100"=> Segment <="0110011";  -- '4' 
        when "0101"=> Segment <="1011011";  -- '5'
        when "0110"=> Segment <="1011111";  -- '6'
        when "0111"=> Segment <="1110000";  -- '7'
        when "1000"=> Segment <="1111111";  -- '8'
        when "1001"=> Segment <="1111011";  -- '9'
        when "1010"=> Segment <="1110111";  -- 'A'
        when "1011"=> Segment <="0011111";  -- 'b'
        when "1100"=> Segment <="1001110";  -- 'C'
        when "1101"=> Segment <="0111101";  -- 'd'
        when "1110"=> Segment <="1001111";  -- 'E'
        when others => Segment <="1001011"; -- 'F'
    end case;

    end if;
end process;


end Behavioral;

Solution

  • There are several mistakes in the code.

    1) Enable is an input, but there are assignments to it. If that signal is for selecting the 7-segment displays, it must be an output.

    Enable: out STD_LOGIC_VECTOR (3 downto 0);
    

    2) Two processes drive the same Segment signal. The assignments should be in one process and they should be multiplexed.

    Create a Select signal and toggle it every clock cycle. You will also need a clock input for that. (Note: I did not show the generation of Select signal)

    process(Bin,Grey)
    begin
    
    if (Select = '0') then -- Select one display
    
            Enable(0) <= '0';
            Enable(1) <= '1';
            Enable(2) <= '0';
            Enable(3) <= '0';
            case Bin is 
            when "0000"=> Segment <="1111110";  -- '0'
            when "0001"=> Segment <="0110000";  -- '1'
            when "0010"=> Segment <="1101101";  -- '2'
            when "0011"=> Segment <="1111001";  -- '3'
            when "0100"=> Segment <="0110011";  -- '4' 
            when "0101"=> Segment <="1011011";  -- '5'
            when "0110"=> Segment <="1011111";  -- '6'
            when "0111"=> Segment <="1110000";  -- '7'
            when "1000"=> Segment <="1111111";  -- '8'
            when "1001"=> Segment <="1111011";  -- '9'
            when "1010"=> Segment <="1110111";  -- 'A'
            when "1011"=> Segment <="0011111";  -- 'b'
            when "1100"=> Segment <="1001110";  -- 'C'
            when "1101"=> Segment <="0111101";  -- 'd'
            when "1110"=> Segment <="1001111";  -- 'E'
            when others => Segment <="1001011"; -- 'F'
        end case;
    
    else -- Select the other display
    
        Enable(0) <= '0';
        Enable(1) <= '0';
        Enable(2) <= '1';
        Enable(3) <= '0';
        case Grey is 
            when "0000"=> Segment <="1111110";  -- '0'
            when "0001"=> Segment <="0110000";  -- '1'
            when "0010"=> Segment <="1101101";  -- '2'
            when "0011"=> Segment <="1111001";  -- '3'
            when "0100"=> Segment <="0110011";  -- '4' 
            when "0101"=> Segment <="1011011";  -- '5'
            when "0110"=> Segment <="1011111";  -- '6'
            when "0111"=> Segment <="1110000";  -- '7'
            when "1000"=> Segment <="1111111";  -- '8'
            when "1001"=> Segment <="1111011";  -- '9'
            when "1010"=> Segment <="1110111";  -- 'A'
            when "1011"=> Segment <="0011111";  -- 'b'
            when "1100"=> Segment <="1001110";  -- 'C'
            when "1101"=> Segment <="0111101";  -- 'd'
            when "1110"=> Segment <="1001111";  -- 'E'
            when others => Segment <="1001011"; -- 'F'
        end case;
    
    end if;
    
    end process;
    

    3) Assert only one bit of Enable signal in a clock cycle and use <= for the assignments. I assumed Enable is active-high. If not, change the values appropriately.

    When display 1 is selected:

    Enable(0) <= '0';
    Enable(1) <= '1';
    Enable(2) <= '0';
    Enable(3) <= '0';
    

    When display 2 is selected:

    Enable(0) <= '0';
    Enable(1) <= '0';
    Enable(2) <= '1';
    Enable(3) <= '0';
    

    4) Enable signal shouldn't be in the sensitivity list. After I merged two processes, it should be as follows.

    process(Bin,Grey)