vhdlfpgaspartan

Using DCM Locked output in Spartan 3 FPGA

I'm using the DCM on the Spartan-3 FPGA which has a LOCKED output signal. I need my clock distributed when it is ready, otherwise it should be zero. Is there any problem with defininga signal which is "CLKOUT and LOCKED" which is used by further entities or do I run into trouble with routing that clock through an and gate?

Solution

  • You're looking for a BUFGCE

    Usually, I use the LOCKED port of a pll to generate the synchronous deassertion reset (RST_N) for my CLK and not for enabling the CLK. It depends on your design which I don't know...

    process (CLK,LOCKED)
begin
  if (LOCKED = '0') then
    rst_n_in <= '0';
    RST_N    <= '0';
  elsif (rising_edge(CLK)) then
    rst_n_in <= '1';
    RST_N    <= rst_n_in ;
  end if;
end process;