fpgaxilinx-ise

force ISE synthesis tool to synthesize a signal

In Xilinx ISE (using VHDL language), I have defined these signals:

signal  counter  : integer range 0 to 24_000_000;
signal  chTriger : std_logic :='0';

and have written the following code:

process_counter: process(clk)
begin 
  if ( clk'event and clk = '1') then
    if (counter < 8192) then
        counter  <= counter + 1;
        chTriger <= not chTriger;
    end if;
  end if;
end process process_counter;`

In ChipScope's select net menu, there is neither a counter nor chTriger signal due to optimization.
How can I force ISE synthesis tool to synthesize a signal?

Solution

  • Read through the Xilinx constraints guide here especially the synthesis constraints. There is one which is called "KEEP".

    In general it is a very useful document to browse if only so you have an idea what you can (and can't do).