Fifo initialization and data transmission in Vitis
I have a relatively simple design, and I’ve attached the diagram below. In short, it’s meant to perform a loop where one core sends data to the FIFO, and another core initializes the DMA and waits to process the incoming data.
Here the address map:
The bitstream is generated correctly, I can export the hardware, and I have successfully created the platform on Vitis. Currently, I've tried sending data by writing the samples to be processed at the base address, but this doesn’t seem to work as expected. Although the data appears to be sent (I see it from the ILA debug core), the AWValid and WValid signals remain low, indicating an issue. I’m also unsure how to handle FIFO fullness checks.
After some research, I found in the documentation (https://docs.amd.com/r/en-US/pg080-axi-fifo-mm-s/Programming-Sequence-Using-Example-Software-Driver) that it may be necessary to initialize the FIFO. However, I noticed that the xllfifo driver wasn’t included in the vitis platform even though the FIFO is present.
The hardware I’m using for this project is a Kria KV 260.
Could anyone guide me on what to do?
Thanks in advance!
I solved it. Having Vivado version 2024.1, until recently I was using the new Vitis Unified IDE. I found that it apparently does not load the fifo drivers, in fact using the classic Eclipse-based Vitis IDE I can see the xllfifo drivers without any problems. I have updated in the question above the block diagram in use.
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