I'm programming a Coolrunner2 (XC2C64A) CPLD with the ISE Project Navigator software. For now, it should only act as a logical or gate (output = o_buzzer) between a pin from a PIC32 (input = i_pic) and a RPi CM3 (input = i_cm).
o_buzzer <= i_pic or i_cm;
The problem is that when the power supply gets connected, the pins of the PIC32 are configured as inputs so the CPLD sees it as high impedance (Z) and outputs a 1 untill the pins are configured. So I'm trying to let the CPLD wait untill i_pic isn't Z anymore.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_gate is
Port ( i_pic : in STD_LOGIC;
i_cm : in STD_LOGIC;
o_buzzer : out STD_LOGIC);
end or_gate;
architecture Behavioral of or_gate is
begin
process_or : process(i_pic,i_cm)
begin
while (i_pic = 'Z') loop
end loop;
o_buzzer <= i_pic or i_cm;
end process process_or;
end Behavioral;
This gives me a warning:
line 46: Loop body will iterate zero times.
And when implementing it doesn't work. Buzzer still beeps till the pins are initialized.
Using the while loop:
while (i_pic = 'Z') loop
o_buzzer <= '0';
end loop;
Gives me:
Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more."
How can I let the process wait untill i_pic is logical low and not Z anymore?
You cannot test for 'Z' in synthesisable code. You can test for a '1' (or 'H') or for a '0' (or 'L'). You cannot test for a 'Z'. What hardware would do this? Some kind of analogue hardware, not some kind of digital hardware. That is why you cannot test for 'Z' in synthesisable code.