vhdlfpgahdlmodelsimasic

Why this process is executed when the simulation starts

This is a simple entity just to know the usage of "process"

My question is: Why the process is executed when the simulation just starts? I think the process wakes up when the signals in the sensitivity list change, but in this example, the assignment to signal 'a' is 3ns after the simulation starts.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;  
use ieee.numeric_std.all;         
use ieee.math_real.all;           

entity test4 is
    port (
        a : in bit;
        f : out bit
    );

end test4;

architecture test4_arc of test4 is
    signal b : bit;
begin

    process(a)
    begin
        report "process triggered";
        
        b <= a;
        f <= not a;
    end process;

end test4_arc;

Here is the testbench

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-----------------------------------------------------------
entity test4tb is
end entity ;
-----------------------------------------------------------
architecture testbench of test4tb  is

   component test4
    port (
        a : in bit;
        f : out bit
    );
   end component;

signal atest,ftest : bit;

begin
    -----------------------------------------------------------
    process
    begin
        wait for 3ns;
        atest <= '0';
        wait for 5ns;
        atest <= '1';
        wait for 5ns;
    end process ;

    dut : test4 port map (
        a => atest,
        f => ftest
    );

end architecture testbench;

message from console of Modelsim

# ** Note: process triggered
#    Time: 0 ns  Iteration: 0  Instance: /test4tb/dut
# ** Note: process triggered
#    Time: 8 ns  Iteration: 1  Instance: /test4tb/dut
# ** Note: process triggered
#    Time: 16 ns  Iteration: 1  Instance: /test4tb/dut
# ** Note: process triggered

enter image description here

Solution

  • All processes will execute at least once at time 0. A process with a sensitivity list is assumed to have a wait on <list> as the last statement in the process. You can read this in VHDL LRM Section 11.3 Process Statement:

    If a process sensitivity list appears following the reserved word process, then the process statement is assumed to contain an implicit wait statement as the last statement of the process statement part; this implicit wait statement is of the form

    wait on sensitivity_list;

    And further in LRM section 14.7.5.2 Initialization:

    f) For each nonpostponed process P in the model, the following actions occur in the indicated order: 1) The process executes until it suspends.

    So all processes will run until they first suspend in the first delta cycle of the simulation. Because processes are actually infinite loops, they have to start somewhere.