[SOLVED] Developing Generic AXI4 Peripheral with Chisel

Developing Generic AXI4 Peripheral with Chisel

I want to develop a generic AXI4 peripheral with Chisel. Can I use the Rocket-Chip's AMBA library for this purpose? I could only find the document in the link below on this subject;

MMIO-Peripherals

However, the example in this document is designed to be used with the Rocket-Chip. I want to develop a standalone AXI4 peripheral.

Solution

Your question mentions following:

I want to develop a standalone Axi4 peripheral

When I had started developing AXI4 interfaces in Chisel, my starting point was the Chisel official documentation where they start with a typical Verilog peripheral using AXI4 for a write channel as following:

 module my_module(
  
// Write Channel
  input        AXI_AWVALID,
  output       AXI_AWREADY,
  input [3:0]  AXI_AWID,
  input [19:0] AXI_AWADDR,
  input [1:0]  AXI_AWLEN,
  input [1:0]  AXI_AWSIZE,
  // ...
);

To this end, the Chisel Bundle would be as following:

class VerilogAXIBundle(val addrWidth: Int) extends Bundle {
  val AWVALID = Output(Bool())
  val AWREADY = Input(Bool())
  val AWID = Output(UInt(4.W))
  val AWADDR = Output(UInt(addrWidth.W))
  val AWLEN = Output(UInt(2.W))
  val AWSIZE = Output(UInt(2.W))
  // The rest of AW and other AXI channels here
}

// Instantiated as
class my_module extends RawModule {
  val AXI = IO(new VerilogAXIBundle(20))
}

Although the aforementioned example is trivial but this was helpful for me to start writing generic AXI4 interfaces in Chisel.

Having said that, I have also used some of the following resources to develop AXI interfaces in Chisel: