Error when instantiating SB_IO_D for Lattice ICE40 for input in VDHL

I'm using the Lattice Ultra ICE5LP. I'm trying to use one of the RGB pins as a regular input (in1_i). I know I have to instantiate SB_IO_OD. I'm using VHDL. I get the error with the Lattice Syntheis tool: in1_i with mode 'in' cannot be updated. VHDL-1358

Why am I getting this error? Here is part of the code (the relevant part):

library sb_ice40_components_syn;
use sb_ice40_components_syn.components.all;

entity design is 
  port (
  ...
    add_i       : in    std_logic_vector(3 downto 0);
    in1_i       : in    std_logic;
    dat_b       : inout std_logic_vector(7 downto 0);
  ...
  );
end design;

architecture rtl_design of design is

  signal sig1_s : std_logic;

....

  PINA6: SB_IO_OD     
    generic map ( NEG_TRIGGER => '0',
                  PIN_TYPE    => "001001" )
    port map ( 
               DIN0 => sig1_s,  -- the internal signal to process and work with.
               OUTPUTENABLE => '0',
               PACKAGEPIN  => in1_i  
               );

PACKAGEPIN is bidirectional. You're trying to connect that to in1_i which is an input. You'll need to use an intermediary signal.