VHDL Vivado: Can I make a variable std_logic_vector from separate std_logic inputs in the test bench?

I'm trying to build an ALU and I want to test it with a loop, the problem is that I have separate std_logic inputs and for a loop I need a vector of the inputs. I tried making a vector of the inputs with variable and I got this error: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

I don't know what this error means, here is my test bench:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity TB_ALU is
--  Port ( );
end TB_ALU;

architecture Behavioral of TB_ALU is
component ALU is
    Port ( INVA, A, ENA, B, ENB, cin, f1, f0: in STD_LOGIC;
           cout : buffer STD_LOGIC;
           output : out STD_LOGIC);
end component;

signal INVA, A, ENA, B, ENB, cin, output, cout, f1, f0 : STD_LOGIC;
begin
U2: ALU port map (INVA=>INVA, A=>A, ENA=>ENA, B=>B, ENB=>ENB, cin=>cin, f1=>f1, f0=>f0, output=>output, cout=>cout);

process
variable input : std_logic_vector(5 downto 0):=(f1, f0, ena, enb, inva, cin);
begin
wait for 10ns;
a<='1'; b<='1';

lp: for i in 0 to 63 loop  
    input := std_logic_vector(to_unsigned(i,6));
    WAIT FOR 10ns;
    end loop lp;
wait;
end process;


end Behavioral;

There should be spaces between 10 and ns (2 occurrences). But your code, that modifies a variable in a loop without any visible side effect, does not really make sense. If your goal is to generate all 64 combinations of your 6 signals with a 10 ns pause between them try:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_alu is
end entity tb_alu;

architecture behavioral of tb_alu is
  component alu is
    port(inva, a, ena, b, enb, cin, f1, f0: in std_ulogic;
         cout: buffer std_ulogic;
         output: out std_ulogic);
  end component;

  signal inva, a, ena, b, enb, cin, output, cout, f1, f0: std_ulogic;
begin

  u2: alu
  port map(inva => inva, a => a, ena => ena, b => b, enb => enb, cin => cin, f1 => f1, f0 => f0, output => output, cout => cout);

  process
  begin
    wait for 10 ns;
    a<='1';
    b<='1';
    lp: for i in 0 to 63 loop  
      (f1, f0, ena, enb, inva, cin) <= std_ulogic_vector(to_unsigned(i,6));
      wait for 10 ns;
    end loop lp;
    wait;
  end process;

end behavioral;

Simple example of left hand side aggregate of signal.

Note the replacement of all std_logic with std_ulogic (as long as you don't know the difference always use std_ulogic, never std_logic).