I've been trying to write VHDL code for a counter. Ultimately, I would like to take the output value, check it with a constant value, and see if the counter has reached the constant value. if it reaches there, I want to reset it. and if not I want to keep counting. What I wrote for the counter process is the following:
CNT: process(clk,reset)
begin
if (reset='0') then
cnt_tmp<= (others=>'0');
elsif (rising_edge(clk)) then
if (enable= '1') then
if (match='1') then
cnt_tmp <= (others => '0');
else
cnt_tmp <= cnt_tmp + 1;
end if;
else
cnt_tmp <= cnt_tmp;
end if;
end if;
end process;
cnt<= cnt_tmp;
So, when the match is 1, we synchronously reset the counter and it also has an enable pin.
This match signal is generated by bitwise xnor the constant with the counter output and "and" of the xnor outputs all together.
However, when I run the simulation, I see some glitches like this:
Does anyone have any idea how can I deal with this problem?
I am expecting to eliminate these glitches even though they don't affect the functionality in my simulations.
Lots going on here:
xnor/and
structure. The inputs will change at slightly different times, so the output glitchesmatch='1'
with a compare against 'the constant'? Glitch gonecnt_tmp
for? It's not necessarycnt_tmp <= cnt_tmp
? That's just pointless extra typingif
statements