When I am writing a module for a bigger project that takes several control input, what is the best practice/standard to handle combinations of input that are invalid or illegal?
For example, I have a Queue that has three control signals - Enqueue, Dequeue and Delete. Assume that only one of the operations can be performed in a cycle. Therefore, only one input signals should be asserted at a time. Now, what is the proper way to handle the case when some parent module drives two control signals at a time?
In my project, I can handle it any way I wish and I will take care to avoid it. But in a company wide level, someone may mess up later and use it improperly. What is the practice to prevent this problem? Or in other words, I am looking for something analogous to try-catch/exception in verilog.
This is a classic example of where an assertion is useful. We don't tend to put error-checking logic in our chips (unless we are designing something safety-critical); instead we use assertions. A property is a potential fact about your design (eg "only one input signal is asserted at a time"). An assertion is a statement that a property should be true.
You can check assertions either using a formal tool or by simulating. In your case, the latter makes sense. So, you would implement a suitable check (the assertion) and then would run all your simulations and make sure that the assertion never fails.
So, how to implement the assertion? How to code it? You could
i) Switch to SystemVerilog. SystemVerilog has an assert statement that is useful for basic assertions and there is a part of SystemVerilog called SystemVerilog Assertions (SVA), which is much more powerful. Verilog is merely a subset of SystemVerilog, but nevertheless switching is still clearly easier said than done - you might need a change in company policy or to buy more expensive licences or some training...
ii) Write assertions in some other language (eg SVA or PSL, but code in Verilog. Again, easier said than done - again you might need a change in company policy or to buy more expensive licences or some training..
iii) Use OVL. This is a free, downloadable library of modules that implement basic (and not so basic) assertions. There is a version written in Verilog, so no company policy change or licences required, but you'd have to invest a bit of time learning how to use them.
iv) Write assertions in Verilog. You could hide them inside generate statements (or ifdefs if you must), to keep them away from the synthesiser, eg:
generate if (ASSERTIONS_ENABLED)
begin : ASSERT_ONLY_ONE_OF_Enqueue_Dequeue_Delete
always @(posedge clock) // it is nearly always better to check assertions synchronously
if (Enqueue + Dequeue + Delete > 2'b1)
$display("ASSERTION FAIL : ASSERT_ONLY_ONE_OF_Enqueue_Dequeue_Delete");
end
endgenerate